1. Field of the Invention
The present invention relates to a memory cell suitable for applications to a highly integrated semiconductor memory and, more particularly, to a capacitor constituting a memory cell and a method of manufacturing the capacitor.
2. Description of the Prior Art
A memory cell (to be referred to as an 1T cell hereinafter) constituted by one transistor and one capacitor is known as a highly integrated semiconductor memory cell. The 1T cell is very popular because it requires a small number of constituent elements and facilitates a reduction in memory cell area.
An output voltage from a 1T cell is proportional to the capacitance value of a capacitor (to be referred to as a cell capacitor hereinafter) constituting a memory cell. For this reason, to assure the stable operation in a highly integrated arrangement, the capacitance value of the cell capacitor must be sufficiently large. To highly integrate 1T cells, cell capacitors each having a sufficiently large capacitance value in a small area are required.
A capacitor using a high-permittivity film, as described in IEDM Technical Digest 1991, pp. 823-826, is known as a typical conventional cell capacitor. This conventional cell capacitor is shown in FIG. 1.
As shown in FIG. 1, the cell capacitor has a silicon substrate 401 having a major surface. A silicon oxide film 402 is formed on the major surface of the silicon substrate 401. A plurality of contact holes are formed in the silicon oxide film 402. Impurity-doped polysilicon members 403 are buried in the plurality of contact holes, respectively. The silicon substrate 401 is electrically connected to a plurality of storage electrodes 406c each consisting of a tantalum film 404c and a platinum film 405c. A high-permittivity film 408c used as a capacitance film is formed on the entire surface including the plurality of storage electrodes 406c and the silicon oxide film 402. A counter electrode 409c is stacked on the high-permittivity film 408c to constitute cell capacitors.
In the above cell capacitors in FIG. 1, a 70-nm thick barium strontium titanate ((Ba.sub.0.5 Sr.sub.0.5)TiO.sub.3) is used as the high-permittivity film 408c, the relative permittivity is 300 or more, and the capacitance value per unit area is 40 fF/.mu.m.sup.2. When this high-permittivity film is applied to a 64-M DRAM cell, a capacitance value of 36 fF is reported in the above reference. It is therefore confirmed that a sufficiently large capacitance value is obtained in a small area.
The platinum film 405c constituting each storage electrode 405c is used to have good antioxidation properties in forming the high-permittivity film 408c. The tantalum film 404c is used to prevent platinum of the platinum film 405c from diffusing into the silicon substrate 401.
In the structure shown in FIG. 1, the high-permittivity film 408c is present between the adjacent storage electrodes 406c. The coupling capacitance between the adjacent storage electrodes 406c is calculated to be as very large as about 2.8.times.10.sup.-15 F according to a plane-parallel approximation. For this reason, in read/write access of information to the cell capacitor, the potential of each storage electrode 406c varies. This potential variation causes noise, and a stable memory operation cannot be obtained.
As a method of solving this problem, there is a cell capacitor cell structure disclosed in Japanese Unexamined Patent Publication No. 4-242971. This technique will be described with reference to FIG. 2. FIG. 2 shows the structure of two memory cells. Each memory cell has a MOS transistor and a capacitor.
The MOS transistor has first and second n-type impurity regions 207 and 208 formed in a p-type silicon substrate 201, and a gate electrode 206 stacked through a gate oxide film 203. The first n-type impurity region 207 serves as one of the source and drain regions. The second n-type impurity region 208 serves as the other of the source and drain regions. A first insulating interlayer 209, a second insulating interlayer 217, and a third insulating interlayer 220 are formed over the gate oxide film 203 and the gate electrode 206 in order as named. A bit line 221 is electrically connected to the second n-type impurity region 208 through a contact hole 240 formed in the first to third insulating interlayers 209, 217, and 220.
The capacitor has a storage electrode 212 connected to the first n-type impurity region 207 through the gate oxide film 203, a counter electrode 214, and a high-permittivity film 213 sandwiched between the storage and counter electrodes 212 and 214. The counter electrode 214 adjacent to the exposed surface is connected to an interconnection 218 through a connection hole 241.
In the memory cell having the above structure, the relative permittivity of the high-permittivity film 213 is set higher than that of the second insulating interlayer 217 to relax concentration of an electric field on the side surfaces of each storage electrode 212, thereby forming a capacitor having a high breakdown voltage. This arrangement is employed to increase the breakdown voltage. In addition, the relative permittivity of the second insulating interlayer 217 is reduced to decrease the coupling capacitance between the capacitors as described above and provide a high resistance against noise. However, since the connection holes. 241 are formed for the counter electrodes 214, respectively, the defects of the connection holes 241 directly cause defective memory cells to decrease the product yield.
A technique for reducing a coupling capacitance between capacitors without forming contact holes, which cause a decrease in product yield, in the respective counter electrodes is disclosed in Japanese Unexamined Patent Publication No. 6-85193. This technique will be described with reference to the accompanying drawings.
FIG. 3 shows the structure of these capacitors. Each capacitor has a storage electrode 306 obtained by stacking tantalum 304 and platinum 305, a high-permittivity film 308 stacked on the storage electrode 306, and a counter electrode 309. An insulating film 307 is formed between the adjacent storage electrodes 306. A silicon substrate 301 is electrically connected to each storage electrode 306 through a polysilicon member 303 buried in a corresponding contact hole formed in a silicon oxide film 302 on the silicon substrate 301. The relative permittivity of the high-permittivity film 308 is set much lower than that of the insulating film 307 to reduce the coupling capacitance between the capacitors. However, a method of manufacturing this capacitor poses a problem which degrades the reliability of the capacitor itself. This manufacturing method will be described with reference to FIGS. 4A to 4E.
First, referring to FIG. 4A, the silicon substrate 301 is thermally oxidized to form the silicon oxide film 302 thereon. Contact holes are formed using the conventional photolithography and dry etching techniques, and polysilicon is grown in these contact holes by the CVD method. In this case, phosphorus is thermally diffused in this polysilicon, and the polysilicon is etched back using dry etching to bury it in the contact holes, thereby forming first conductive members 303.
Referring to FIG. 4B, the tantalum film 304 and the platinum film 305 are stacked on the entire surface by sputtering. Barium strontium titanate ((Ba.sub.0.5 Sr.sub.0.5)TiO.sub.3) is grown at a growth temperature of 650.degree. C. by RF magnetron sputtering to form the high-permittivity film 308. A storage electrode formation resist film 310 is then formed by conventional photolithography.
Referring to FIG. 4C, the high-resistivity film 308, the platinum film 305, and the tantalum film 304 are etched by dry etching, and the resist film 310 is removed. Each storage electrode 306 is constituted by the tantalum film 304 and the platinum film 305.
Referring to FIG. 4D, the insulating film 307 consisting of a silicon oxide film is buried and deposited by CVD to planarize the upper surface to a desired degree.
Referring to FIG. 4E, the insulating film 307 is etched back by dry etching until the upper surface of the insulating film 307 is leveled with the upper surface of the high-permittivity film 308. By this etch-back process, the surface of the high-permittivity film 308 is perfectly exposed, and the film quality is degraded. That is, the high-permittivity film 308 is damaged by etching, and an impurity is mixed therein. Then the counter electrode 309 consisting of a titanium nitride film is stacked on the entire surface to obtain the capacitors shown in FIG. 3.
In this structure, the connection holes (contact holes) need not be formed in units of capacitors, unlike the above prior art, and the number of manufacturing steps can be reduced, thereby preventing a decrease in product yield in this respect. However, since the surface of the high-permittivity film 308 is exposed to an etching atmosphere which degrades the film quality, the reliability of the device is degraded as a whole.